MODELING THE TRANSIENT RESPONSE OF CHANNEL-SUBSTRATE INTERFACE TRAPS TO GATE VOLTAGE STEPS IN GaAs FETs

Abstract

The transient response of a hole trap, located in the substrate (buffer) side of the channelsubstrate interface in GaAs FETs, to a pulse applied to the gate is accurately modelled. The modelled transient is found to be non-exponential and in excellent agreement with the experimental data. The similarity between the filling and emptying rates of the traps is explained in terms of the very close position of the Fermi level in the substrate (buffer), where the trap is located, to that of the trap level