Study of thin film transistors (TFTs) based on In, Sn and Zn amorphous oxides alloys

Abstract

This work is mainly focused on a numerical optimization of a-ITZO TFT based on the gate dielectric materials. Different types of high-k gate dielectrics are proposed. The effect of the thickness of : the double-layered dielectric, the equivalent oxide and the mono-layered dielectric of the gate is also presented. In addition, the effect of the interfacial states that can subsist between the TFT channel and the gate dielectric is also studied, for first low-k dielectrics such as SiO2 and second for high-k dielectrics such as Al2O3. Accurate analyses were implemented through numerical simulation of the device by Silvaco Atlas software that was used to carry out a detailed numerical analysis for investigating the relationship between these different effects and the performance and reliability of the device. The results showed that replacing the low-k SiO2 layer by a high-k dielectric layer in TFT based on the mono-layered dielectric leads to attractive improvements in the performance of a-ITZO TFT similar to the improvements resulting from the decrease in the physical thickness of the gate dielectric without the associated leakage effects. Also, the TFT device based on the double-layered dielectric (SiO2/HfO2) with a higher thickness (DDT = 70 nm) it can provide the same electrical properties that are offered by TFT device based on the equivalent oxide with a less thickness, almost seven times (EOT = 10 nm), without the associated leakage effects, while provides electrical properties better than properties that are offered by TFT based on the mono-layered dielectric (SiO2), for the same thickness (MDT = 70 nm). In addition, the TFT device based on the double-layered dielectric (Al2O3/HfO2) with a physical thickness (PT = 30 nm) it can provide good electrical properties better than the properties provided by TFT based on the double-layered dielectric (SiO2/HfO2) for the same physical thickness. However, it we cannot neglect the fundamental role of the interfacial low-k SiO2 layer between the channel and the high-k dielectric, which has some beneficial qualities with regard to the carrier mobility in the transistor channel. Also, although there is a difference in the value of leakage between the two devices, its effect is very poor on the performance of the device and its reliability, especially for low gate tensions.